Matias Segura is a Master’s student in Computer Engineering at the University of Central Florida. He is continuing his educational career as part of the B.S. to M.S. accelerated program at UCF. Matias has a strong interest in VLSI Verification Methodologies, VLSI Design, FPGAs, and Computer Architecture. He joined the lab to deepen his knowledge in Formal Verification Methods and looks forward to help develop new technologies in the field.
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