Projects
Our research spans hardware security, side channel analysis, AI-assisted vulnerability assessment, secure autonomous systems, and cryptographic design. Each project below is backed by real partnerships, produces open deliverables, and trains the next generation of security engineers.
Every active project takes undergraduate and graduate researchers. Pick the one whose question you want to answer, then get in touch — and if you are after a two-semester capstone instead, see Senior Design.
Biology coordinates groups with no leader, no clock, and no reliable channel — and it does it while under attack. SHARKS translates those mechanisms into swarm algorithms, tests them across a portfolio of missions rather than a single task, and measures what an adversary inside the group can do to each one.
Hardware leaks what software is doing. Shadow AI fingerprints workloads from power and electromagnetic side channels alone, without instrumenting the host — identifying what is running on a machine you do not control.
Given an observed artifact or signal, which model produced it? Trace-AI carries Shadow AI’s fingerprinting from what is running to what ran, building attribution evidence that survives the gap between execution and observation.
Edge ML accelerators leak their models. Aegis measures how much of a deployed network — architecture, weights, inputs — an attacker can recover from side channels alone, then builds the countermeasures that close the gap.
Verilog hides its own dataflow. RTL Insight builds on Yosys to extract, analyze, and visualize the structure of large designs, giving engineers a way to reason about logic that has outgrown what anyone can read top to bottom.
Formal verification stalls on state explosion long before it reaches production-scale RTL. Dark Logic attacks that cost directly — abstraction, decomposition, and invariant discovery that shrink what model checkers and theorem provers must actually prove.
Digital verification never looks at the PLL. Dark Matter studies malicious modification hidden in analog and mixed-signal blocks — clocking, data conversion, power management — where the digital toolchain is structurally blind.
A peer-to-peer IoT network built on the CHIRP communication algorithm, aimed at devices too small for a conventional stack. We are measuring what the protocol costs in power, memory, and latency once it leaves simulation and lands on real radios.
A modified cryptosystem that permits computation directly on encrypted data, paired with the accelerator that makes it practical. The target is stronger than computing on plaintext and fast enough that fully homomorphic encryption is not the only option.
Building on the E3X ISA for partially homomorphic execution, we are moving side-channel-resistant architecture off the simulator and into hardware — where timing, power, and area decide whether the guarantees survive contact with silicon.
Entropy is a cheap proxy for switching activity. Signal Insight tests how far information-theoretic measures can substitute for simulation in estimating power, and whether the same measures can steer optimization rather than only report on it.
Borrowed from malware evasion — fundamental logic components that compute standard operations under a continuously changing key, so the implementation an attacker profiles is never the implementation that runs next.
Past Projects
Work that has run its course. The questions are answered, the students have graduated, and the results live on in publications and in the people who did them.
Trojan insertion across the FPGA development lifecycle, from HDL through bitstream, asking how far an AI-generated attacker could degrade performance and efficiency while staying invisible until it fires.
A methodology for detecting hardware Trojans from side-channel measurements using machine learning, evaluated across a range of Trojan designs and trigger conditions.
An assessment of where memristor-based devices are vulnerable, and what countermeasures are available to a designer building on them.
An FPGA system that writes a pattern to a memristor, reads it back, and compares the two — the test harness the memristor security work depended on.
Recovering structure from raw scan-chain dumps, so that regions worth attention can be located without a golden reference model of the whole design.
Formal equivalence checking between a verified and an unverified RISC-V processor, run by undergraduate researchers as both a verification exercise and a teaching one.
Whether the edge-side hardware that accelerates homomorphic encryption leaks its own cryptographic keys through the side channels the scheme was meant to make irrelevant.
Whether an STM32 microcontroller running a real-time operating system holds both data integrity and real-time guarantees under a clock glitching attack.
Canaries embedded in a home router that identify targeted hardware, surface the addresses involved, and isolate a compromised IoT device before it can be used further.